Various types of AD conversion systems are known, such as flash, successive approximation and pipeline, slope and follow-up, double integral (double slope type), VF conversion, and Delta Sigma. A successive approximation register analog-to-digital converter (SAR-ADC) is characterized in having a simple circuit configuration and low power consumption because no operational amplifier is necessary for analog signal processing. SAR-ADC is used widely in combination with a microcomputer etc.
SAR-ADC is implemented by a configuration that uses a digital-to-analog converter (DAC) that changes a current value, a configuration that utilizes a capacitive DAC (hereinafter, referred to as CDAC) having a plurality of sub capacitors the capacitance values of which change in a ratio of powers of 2, etc. In recent years, a configuration that utilizes CDAC is common and in the following explanation, the configuration that utilizes CDAC is explained as an example.
In a SAR-ADC that utilizes CDAC, an analog input signal is sampled by the CDAC and a charge amount corresponding to the voltage value of the analog input signal is held in the CDAC. The voltage value of the CDAC is compared with a reference potential by a comparator and the determination result is output, and in accordance with the determination result, reference voltages to be applied to the terminals of the sub capacitors forming the CDAC, i.e., bit values corresponding to the sub capacitors are determined so that the voltage value of the CDAC becomes close to the reference potential. The voltage of the CDAC having changed accompanying the determination of the sub capacitor is further compared by the comparator and a loop operation to cause a change so that voltage value of the CDAC further becomes close to the reference potential is repeated. By repeating the loop operation for the sub capacitors in the order from the sub capacitor having the largest capacitance value, the voltage of the CDAC asymptotically approaches the reference potential.
In the case of a k-bit ADC, (k+1) sub capacitors whose capacitance value ratio is 1:1:2:4: . . . :2k-1 are provided and determination is performed sequentially in the order from the bit value corresponding to the sub capacitor having the largest capacitance value. That is, at the point of time when the determination of k bits is completed, a digital signal (data) indicating the digital level closest to the voltage value of the analog signal, i.e., indicating the voltage value at the 2k interval for the full scale voltage is determined. A voltage difference between the actual voltage of the analog input signal and the voltage value indicated by the digital signal is referred to as a residual voltage and the range of the residual voltage is a so-called quantization error.
As described above, in the SAR-ADC, the loop operation for determination is repeated the number of times corresponding to the resolution of the ADC sequentially in the order from the loop operation for determination of the highest-order bit. For example, in the case where the resolution of the ADC is 12 bits (k=12), the determination loop is repeated 12 times. Due to this, AD conversion of the sampled analog input signal is completed.
In the SAR-ADC, the CDAC and the comparator are used repeatedly by the loop operation, and therefore, it is necessary to preserve the analog input signal once sampled as charges in the CDAC until the AD conversion of k bits is completed. Consequently, the conversion period of the SAR-ADC is the sum of the sampling time and the AD conversion time for k bits.
The AD conversion time is proportional to the number k of bits (resolution). That is, if the relatively short sampling time is ignored, the conversion speed, which is the inverse of the conversion period, is inversely proportional to the resolution k.
The SAR-ADC that uses the CDAC is characterized in having a simple circuit configuration and low power consumption because no operational amplifier is necessary for analog signal processing.
In recent years, improvement in conversion speed is demanded also for the SAR-ADC. By reducing the loop time for one-time loop operation, the conversion speed is expected to improve, however, there is a limit to this method in view of the response and settling time of the comparator and CDAC.
The SAR-ADC is implemented by a simple configuration and has an architecture excellent in low power consumption, however, there is a problem that if one of the resolution and conversion speed is increased, the other reduces inevitably.